1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same and, in particular, to a configuration of a surface of a conductive region and a manufacturing method of the same.
2. Description of the Background Art
First, an interconnection structure between a conductive region and an interconnection layer in the prior art will be described below.
FIG. 49 is a schematic cross section showing a connection structure between the conductive region and the interconnection layer in the prior art. Referring to FIG. 49, a MOS (Metal Oxide Semiconductor) transistor 410 is formed in a region of a silicon substrate 401 isolated by an isolating oxide film 403.
The MOS transistor 410 includes a pair of source/drain diffusion regions 409, a gate oxide film 405 and a gate electrode 407. The pair of source/drain diffusion regions 409 are formed on a surface of the silicon substrate 401 with a predetermined space between each other. The gate electrode 407 is formed on a region located between the pair of source/drain diffusion regions 409 with the gate oxide film 405 therebetween. The gate electrode 407 is covered with an insulating film 411.
The MOS transistor 410 is covered with an interlayer insulating film 413 which is formed on the entire surface of the silicon substrate 401. The interlayer insulating film 413 is provided with a contact hole 413a, through which a surface of the source/drain diffusion region 409 is partially exposed. There is formed an interconnection layer 417, which is in contact with the surface of the source/drain diffusion region 409 through the contact hole 413a.
Following disadvantages are caused in the conventional connection structure shown in FIG. 49 due to high integration.
In accordance with miniaturization of elements for the high integration, the conductive regions such as source/drain diffusion regions 409 are inevitably reduced in sizes. Therefore, the contact hole 413a for exposing the surface of the conductive region 409 is reduced in diameter. Accordingly, a contact portion 415a between the interconnection layer 417 and conductive region 409 has a reduced area.
In general, a resistance of the contact portion 415a between the interconnection layer 417 and conductive region 409 depends on the area of the contact portion 415a, and decreases in accordance with the increase of the area. In general, the electric resistance of the contact portion 415a must be about 100.OMEGA. or less. However, the contact portion 415a, of which area is reduced due to the miniaturization of the elements for the high integration, has a high resistance in a range from several hundreds .OMEGA. to several thousands .OMEGA.. The high resistance of the contact portion 415a reduces a current driving capability, and thus reduces an amount of electric charges sent to an element or circuit of the succeeding stage. This reduces operation speed of the element or circuit, and may disable the operation of the element or the like in the worst case.
The above disadvantages due to the high integration may be prevented by the following interconnection structures.
(1) As shown in FIG. 50, a contact portion 415b between the interconnection layer 417 and conductive region 409 has an irregular or uneven configuration, whereby a large contact area is ensured between the interconnection layer 417 and conductive region 409.
(2) As shown in FIG. 51, a local interconnection layer 415c is formed between the interconnection layer 417 and conductive region 409, whereby an area for the contact with the interconnection layer 417 is increased.
In FIGS. 50 and 51, portions corresponding to those in FIG. 49 bear the same reference numerals. The local interconnection layer 415c described in the above item (2) is a conductive layer provided merely between the conductive region 409 and interconnection layer 417.
The method for forming the uneven surface of the semiconductor substrate described in the above item (1) is disclosed in Japanese Patent Laying-Open Nos. 3-280532 (1991) and 4-26153 (1992).
More specifically, Japanese Patent Laying-Open No. 3-280532 discloses a manufacturing method of a semiconductor device having an uneven connection portion between the conductive region and interconnection layer. The manufacturing method will be described below.
FIGS. 52-55 are schematic cross sections showing steps in the manufacturing method of the semiconductor device disclosed in the publication. Referring to FIG. 52, a MOS transistor 510, which includes a pair of source/drain diffusion regions 509, a gate oxide film 505 and a gate electrode 507a, is formed in a region of a silicon substrate 501 isolated by isolated oxide films 503. Thereafter, a protective oxide film 511 covering the MOS transistor 510 is formed on the entire surface of the silicon substrate 501. A photoresist is applied to the surface of the protective oxide film 511, and is patterned, e.g., by photolithography to form a resist pattern 513 having an intended configuration. Using the resist pattern 513 as a mask, etching is effected on the protective oxide film 511. The protective oxide film 511 has contact holes 511a through which the surfaces of the source/drain diffusion regions 509 are partially exposed. Then, the resist pattern 513 is removed.
Referring to FIG. 53, a resist film 515 containing silica film (SOG) is formed by spin coating of mixture liquid of the silica film and thin organic film such as photoresist.
Referring to FIG. 54, anisotropic etching with oxygen plasma is carried out for removing resist component of the resist film 515 containing the SOG, using particles of SOG as a mask 515a. Using the pattern of the particles as the mask 515a, the etching is effected on the surfaces of the silicon substrate 501 exposed through the contact holes 511a.
Referring to FIG. 55, thus the surfaces exposed through the contact holes 511a come to have unevenness 519. Thereafter, the mask 515a is removed. A sputter method is used to deposit an aluminum silicon (AlSi) thin film 517, which is in contact with the source/drain diffusion regions 519 having uneven surfaces through the contact holes 511a. The thin film 517 is patterned, e.g., by photolithography to form an intended interconnection pattern.
In Precedings of Joint Lectures of 36th Institution of Applied Physics 1989, vol. 2, p. 668, making the surface uneven by a similar method as that disclosed in Japanese Patent Laying-Open No. 3-280532 is disclosed. More specifically, an oxide film and a polycrystalline silicon film are deposited stacked in this order on a silicon substrate, and the surface of the polycrystalline silicon film is made rough by the above described method. The shape of the unevenness formed on the surface of the polycrystalline silicon film has the width of in the range from 0.1 to 0.8 .mu.m and the depth of from 0 to 0.6 .mu.m.
Japanese Patent Laying-Open Publication No. 4-26153 discloses a structure of a semiconductor device which is provided with trenches having uneven surfaces, and a manufacturing method of the same. The structure of the semiconductor device disclosed in this publication may be applied to a memory cell of a trench type, e.g., in a DRAM (Dynamic Random Access Memory). A general structure of the memory cell of the trench type DRAM will be described below.
FIG. 56 is a schematic cross section showing the general structure of the memory cell of the trench type in the DRAM. Referring to FIG. 56, a memory cell of the one-transistor and one-capacitor type is generally employed in the DRAM. Thus, it employs a structure in which one capacitor 620 is electrically connected to one transfer gate transistor 610. This memory cell is formed in a region of a silicon substrate 601 isolated by an isolating oxide film 603.
The transfer gate transistor 610 includes a pair of source/drain diffusion regions 607, a gate oxide film 605a and a gate electrode 617. The pair of source/drain diffusion regions 607 are spaced from each other by a predetermined distance. The gate electrode 617 is formed on a region located between the pair of source/drain diffusion regions 607 with the gate oxide film 605a therebetween.
The capacitor 620 includes the impurity diffusion region 607, a capacitor dielectric film 609 and an electrode layer 611. The silicon substrate 601 is provided with a trench 601b. On the surface of the trench 601b, there is formed the impurity diffusion region 607 which forms one of the electrodes. This impurity diffusion region 607 is formed of one of the source/drain diffusion regions 607, and is electrically connected to the transfer gate transistor 610. The surface of the impurity diffusion region 607 formed on the surface of the trench 601b is covered with a thin capacitor dielectric film 609. The trench 601b is filled with an electrode layer 611, which forms the other of the electrodes and is opposed to the impurity diffusion region 607 with the capacitor dielectric film 609 therebetween. The capacitor 620 is covered with an insulating film 613.
A method for forming the uneven surface of the trench shown in the Japanese Patent Laying-Open No. 4-26153 will be described below.
FIGS. 57-60 are schematic cross sections showing steps in a method for forming the uneven surface of the trench disclosed in the above publication. Referring to FIG. 57, anisotropic plasma etching is effected to a silicon substrate 701 to form a trench 701a. A photoresist 703 is applied to the surface of the silicon substrate 701 and trench 701a. The photoresist 703 is patterned, e.g., by exposure. This exposure is carried out with g-ray (436 nm) and a stepper equipped with NA0.35 lens.
Referring to FIG. 58, the photoresist 703 located on side surfaces of the trench 701a is patterned into wavy forms by standing waves, caused by interference of progressive wave of exposure beam and reflected wave from a wafer during the exposure. A distance between peaks of the wavy form is about 0.2 .mu.m.
Referring to FIG. 59, isotropic etching is effected on silicon, which forms the side surfaces of the trench 701a, with plasma of CF.sub.4 +O.sub.2. As a result, the trench 701b has the wavy and uneven surfaces at it sides and bottom. Thereafter, the photoresist mask 703b is removed, so that the unevenness is formed on the surface of the trench 701b, as shown in FIG. 60.
As described above, the methods for forming the uneven and rough surface of the semiconductor substrate have been disclosed in the Japanese Patent Laying-Open Nos. 3-280532 and 4-26153.
In the method disclosed in Japanese Patent Laying-Open No. 3-280532, however, it is difficult to determine how the silica film and organic thin film are mixed in the resist 515 containing the SOG. It is particularly difficult to determine the state of mixture when the resist has been applied onto the substrate 501. It is also difficult to control the state of mixture of the silica film and organic thin film-to be an intended state. Therefore, even in the case when only the resist component is removed from the resist 515 and that the particles of SOG are used as the mask 515a, it is very difficult to leave the particles of SOG to have the intended form. For this reason, it is difficult to control the configuration of the unevenness 519 which is formed with the mask 515a formed of the particles of SOG.
In the method disclosed in Japanese Patent Laying-Open No. 4-26153, the exposure beams behave in a complicated manner in the photoresist 703 during the exposure. Therefore, it is difficult to estimate a relationship such as the interference of the progressive wave of exposure beam and the reflected wave from the wafer. For this reason, it is very difficult to control the photoresist 703 for forming the intended uneven configuration by the exposure. Therefore, it is difficult to control the unevenness of the surface of the trench 701b to have the intended configuration.
In the methods disclosed in the publications described above, it is difficult to form the intended uneven surface of the silicon substrate under precise control. Therefore, it is difficult to reduce a contact resistance between the interconnection layer and conductive region and to increase the capacitor capacity under precise control.
In the case when the local interconnection layer 415c is provided, as shown in FIG. 51, a relatively large contact area can be ensured between the interconnection layer 417 and local interconnection layer 415c. Therefore, it is possible to suppress the increase of the contact resistance due to the reduction of the contact area. However, the provision of the local interconnection layer 415c between the interconnection layer 417 and conductive region 409 increases the number of contacts. In other words, the two contact portions are formed between the local interconnection layer 415c and interconnection layer 417 and between the local interconnection layer 415c and conductive region 409 when the local interconnection layer 415c is provided, while only one contact portion is formed between the interconnection layer 417 and conductive region 409 when the local interconnection layer 415c is not provided. The provision of the local interconnection layer 415c increases the number of contacts, and thus increases the contact resistance.